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Preliminary 2
Typical Applications * 3V CDMA/AMPS Cellular Handsets * 3V JCDMA Cellular Handsets * 3V CDMA2000 Cellular Handsets
RF2192
3V 900MHZ LINEAR POWER AMPLIFIER
* 3V TDMA/GAIT Cellular Handsets * Spread-Spectrum Systems * Portable Battery-Powered Equipment
2
POWER AMPLIFIERS
Product Description
3.75
2 0.45 0.28 0.75 0.50 0.80 TYP 1
1
The RF2192 is a high-power, high-efficiency linear amplifier IC targeting 3V handheld systems. The device is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been designed for use as the final RF amplifier in dual-mode 3V CDMA/AMPS and CDMA2000 handheld digital cellular equipment, spread-spectrum systems, and other applications in the 800MHz to 960MHz band. The RF2192 has a low power mode to extend battery life under low output power conditions. The device is packaged in a 16 pin, 4mmx4mm leadless chip carrier.
3.75
+
1.60 4.00
12 1.50 SQ 3 INDEX AREA 3.20 4.00 1.00 0.90
0.75 0.65
NOTES:
1 Shaded Pin is Lead 1. 2 Dimension applies to plated terminal and is measured 0.10 mm and 0.25 mm from terminal tip.
0.05 0.00
Dimensions in mm.
The terminal #1 identifier and terminal numbering conv 3 shall conform to JESD 95-1 SPP-012. Details of termin identifier are optional, but must be located within the z indicated. The identifier may be either a mold or marke feature. 4 5 Pins 1 and 9 are fused. Package Warpage: 0.05 max.
Optimum Technology Matching(R) Applied
Si BJT Si Bi-CMOS
u
Package Style: LCC, 16-Pin, 4x4
GaAs HBT SiGe HBT
VCC BIAS
GaAs MESFET Si CMOS
Features * Single 3V Supply * 29dBm Linear Output Power * 37% Linear Efficiency * Low Power Mode * 45 mA idle current * 47% Peak Efficiency 31dBm Output
VCC1
VCC1
GND
1 GND 2 GND 3 RF IN 4 5 VREG1
16
15
14
13 12 RF OUT 11 RF OUT 10 RF OUT
6 VMODE
7 VREG2
8 BIAS GND
9 GND
2F0
Ordering Information
RF2192 RF2192 PCBA 3V 900MHz Linear Power Amplifier Fully Assembled Evaluation Board
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
Rev A1 010830
2-203
RF2192
Absolute Maximum Ratings Parameter
Supply Voltage (RF off) Supply Voltage (POUT 31dBm) Mode Voltage (VMODE)
Preliminary
Rating
+8.0 +5.2 +4.2
Unit
VDC VDC VDC Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
2
POWER AMPLIFIERS
Control Voltage (VREG) Input RF Power Operating Case Temperature Storage Temperature Moisture Sensitivity
+3.0 VDC +10 dBm -30 to +110 C -30 to +150 C Modified JEDEC Level 2
Parameter
High Power State (VMODE Low)
Frequency Range Linear Gain Second Harmonic Third Harmonic Maximum Linear Output Power (CDMA Modulation) Total Linear Efficiency Adjacent Channel Power Rejection Input VSWR Output VSWR Noise Power
Specification Min. Typ. Max.
Unit
Condition
Case T=25C, VCC =3.4V, VREG = 2.85V, VMODE =0V to 0.5V, Freq=824MHz to 849MHz (unless otherwise specified)
824 27
849 30 -33 <-60
29 37 -48 -58 2:1
MHz dB dBc dBc dBm % dBc dBc POUT =29dBm ACPR @885kHz ACPR @1980kHz No damage. No oscillations. >-70dBc At 45MHz offset Case T=25 C, VCC =3.4V, VREG =2.85V, VMODE =1.8V to 3V, Freq=824MHz to 849MHz (unless otherwise specified)
-44 -56 10:1 6:1
-133
dBm/Hz
Low Power State (VMODE High)
Frequency Range Linear Gain Second Harmonic Third Harmonic Maximum Linear Output Power (CDMA Modulation) Max ICC Adjacent Channel Power Rejection Input VSWR Output VSWR 824 19 849 22 -33 <-60 20 150 -48 <-60 2:1 MHz dB dBc dBc dBm mA dBc dBc
16
-46 -58 10:1 6:1
POUT =+16dBm (all currents included) ACPR @885kHz ACPR @1980kHz No damage. No oscillations. >-70dBc
2-204
Rev A1 010830
Preliminary
Parameter
High Power State CDMA 2000 1x (VMODE LOW)
Frequency Range Linear Gain Pilot+DCCH 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection Pilot+FCH 9600+SCHO 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection 824 29 26.5 -47 <-60 29 -47 <-60 849 MHz dB dBm dBc dBc dBm dBc dBc
RF2192
Specification Min. Typ. Max. Unit Condition
Case T=25oC, VCC =3.4V, VREG =2.85V. VMODE =0V to 0.5V, Freq=824MHz to 849MHz (unless otherwise specified)
2
2.5dB Backoff included in IS98D CCDF 1% 5.4dB Peak Average Ratio at CCDF 1% ACPR@ 885kHz ACPR@ 1.98MHz 4.5dB Peak Average Ratio at CCDF 1% ACPR@ 885kHz ACPR@ 1.98MHz Case T=25oC, VCC =3.4V, VREG =2.85V. VMODE =1.8V to 3V, Freq=824MHz to 849MHz POWER AMPLIFIERS
Low Power State CDMA 2000 1x (VMODE HIGH)
Frequency Range Linear Gain Pilot+DCCH 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection Efficiency Pilot+FCH 9600+SCHO 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection 824 22 16 20 -48 <-85 15 16 20 <-50 <-65 849 MHz dB dBm dBc dBc % dBm dBc dBc
5.4dB Peak to Average Ratio at CCDF 1% ACPR@ 885kHz ACPR@ 1.98MHz POUT =20dBm 4.5dB Peak to Average Ratio at CCDF 1% ACPR@ 885kHz ACPR@ 1.98MHz Case T=25C, VCC =3.4V, VREG =2.85V, VMODE =0V to 0.5V, Freq=824MHz to 849MHz (unless otherwise specified)
FM Mode
Frequency Range Gain Second Harmonic Third Harmonic Max CW Output Power Total Efficiency (AMPS mode) Input VSWR Output VSWR 824 30 -33 <-60 32 47 2:1 10:1 6:1 849 MHz dB dBc dBc dBm %
31
POUT =31dBm (room temperature) No damage. No oscillations. >-70dBc
Note: DCCH: Dedicated Control Channel FCH: Fundamental Channel CCDF: Complementary Cumulative Distribution Function
Rev A1 010830
2-205
RF2192
Parameter
DC Supply
Supply Voltage Quiescent Current 3.0 3.4 160 45 4.2 V mA mA mA mA s
Preliminary
Specification Min. Typ. Max. Unit Condition
The maximum power out for VCC =3.0V is 28dBm. VMODE =Low VMODE =High
2
POWER AMPLIFIERS
VREG Current VMODE Current Turn On/Off Time
70 10 1 <40
Total Current (Power Down) VREG "Low" Voltage VREG "High" Voltage VMODE "Low" Voltage VMODE "High" Voltage
0 2.75 0 1.8
2.85 2.85
10 0.5 2.95 0.5 3.0
A V V V V
Time between VREG turned on and PA reaching full power. Turn on/off time can be reduced by lowering the bypass capacitor value on the VREG line. VREG =Low
2-206
Rev A1 010830
Preliminary
Pin 1 2 3 4 Function GND GND GND RF IN Description
Ground connection. Ground connection. Ground connection. RF input. An external 100pF series capacitor is required as a DC block. In addition, shunt inductor and series capacitor are required to provide 2:1VSWR.
RF IN
RF2192
Interface Schematic
VCC1 100 pF From Bias GND1 Stages
2
POWER AMPLIFIERS
5 6 7 8 9 10
VREG1 VMODE VREG2 BIAS GND GND RF OUT
Power Down control for first stage. Regulated voltage supply for amplifier bias. In Power Down mode, both VREG and VMODE need to be LOW (<0.5V). For nominal operation (High Power Mode), VMODE is set LOW. When set HIGH, the driver and final stage are dynamically scaled to reduce the device size and as a result to reduce the idle current. Power Down control for the second stage. Regulated voltage supply for amplifier bias. In Power Down mode, both VREG and VMODE need to be LOW (<0.5V). Bias circuitry ground. See application schematic. Ground connection. RF output and power supply for final stage. This is the unmatched collector output of the second stage. A DC block is required following the matching components. The biasing may be provided via a parallel L-C set for resonance at the operating frequency of 824MHz to 849MHz. It is important to select an inductor with very low DC resistance with a 1A current rating. Alternatively, shunt microstrip techniques are also applicable and provide very low DC resistance. Low frequency bypassing is required for stability. Same as pin 10. Same as pin 10. Harmonic trap. This pin connects to the RF output but is used for providing a low impedance to the second harmonic of the operating frequency. An inductor or transmission line resonating with an on chip capacitor at 2fo is required at this pin. Power supply for bias circuitry. A 100pF high frequency bypass capacitor is recommended. Power supply for first stage. Same as Pin 15. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground plane.
RF OUT
From Bias Stages
11 12 13
RF OUT RF OUT 2FO
See pin 10.
14 15 16 Pkg Base
VCC BIAS VCC1 VCC1 GND
Rev A1 010830
2-207
RF2192
Evaluation Board Schematic US - CDMA
(Download Bill of Materials from www.rfmd.com.)
VCC C2 4.7 uF C6 100 pF C28 10 nF C4 100 pF
Preliminary
2
POWER AMPLIFIERS
C25 4.7 F C30 TL3
L5 1 nH
TL5 1 C9 100 pF R2 510 C24 12 pF C27 100 pF R3 0 R4 0 L4 39 nH Board CDMA (US) Transmission Line Length CDMA (US) C30 (pF) 100 C1 (pF) 9.1 L1 (nH) 20 C14 (pF) 9.1 2 3 4 L2 5.6 nH 5 6 7 8 16 15 14 13 12 11 10 9
* L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1 and C14 are High Q capacitors (i.e., Johanson C-series).
L1*
C17 2.4 pF C3 100 pF
TL1
TL2 C1**
J1 RF IN
C5 100 pF
J4 RF OUT
C14**
C26 4.7 F VREG VMODE R1 0
C13 100 pF
TL1 15 mils
TL2 350 mils
TL3 105 mils
TL5 85 mils
2-208
Rev A1 010830
Preliminary
Evaluation Board Layout 2.0" x 2.0"
RF2192
Board Thickness 0.031", Board Material FR-4, Multi-Layer, Ground Plane at 0.015"
2
POWER AMPLIFIERS
Rev A1 010830
2-209
RF2192
Preliminary
2
POWER AMPLIFIERS
2-210
Rev A1 010830

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